Analog to digital conversion by subranging with multiple level redundant error correction

ABSTRACT

An analog to digital converter apparatus utilizing subranging with multiple level redundant error correction to increase the speed of conversion. The multiple level correction technique provides a more rapid acquisition of the subrange word.

United States Patent m1 ,891,984

Kerwin et al. June 24, 1975 I54] ANALOG TO DIGITAL CONVERSION BY 3,483,550 l2/l969 Max 340/347 AD SUBRANGING WITH MULTIPLE LEVEL REDUNDANT ERROR CORRECTION OTHER PUBLICATIONS [75 l Inventors: Robert Kerwin} Orange; Darwin Hoeschele, "Analog-to-Digital[Digital-to-Analog Sulzle placgmla' both 6f Cahf' Conversion Techniques," 8/1968, J. Wiley & Sons, [73] Assignee: The United States of America as PP- represented by the Secretary of the Force Washington Primary E \'aminerThomas J. Sloyan [22] Filed: Mar. 7, 1973 Attorney, Agent, or FirmWilliam Stepanishen [2]] Appl. No.: 338,727

[52] US. Cl... 340/347 CC; 324/99 D; 340/347 AD [57] ABSTRACT [5|] Int. Cl. H031 13/02 An analog to digital convermr apparatus utilizing [58] held Search 340/347 347 CC; ranging with multiple level redundant error correction 324/99 D to increase the speed of conversion. The multiple level correction technique provides a more rapid acquisi- [56] References tion of the subrange word.

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I i l KIN l I5 1 l i l I I 1 ANALOG TO DIGITAL CONVERSION BY SUBRANGING WITH MULTIPLE LEVEL REDUNDANT ERROR CORRECTION BACKGROUND OF THE INVENTION The present invention relates broadly to an analog to digital converter apparatus and in particular to a subranging analog to digital converter with multiple level redundant error correction.

In the prior art various techniques and schemes have been utilized to increase the speed of analog to digital converters. Analog to digital converter can usually be classified into groups. One group includes high speed parallel converters in which the several digital bits are formed more or less simultaneously. The high speed of operation is obtained here at significant expenditures. The converters of the second group operate by successive approximation; progressively synthesized analog equivalents of progressively formed digital signals are compared individually with the analog information signal.

A digital correction scheme which is known in the prior art as single level correction, has been used with a subranging converter of three or more subrange stages. This technique is used to overcome the basic limitations in the comparator threshold accuracies and the interim D/A amplifier settling times. Single level correction will approximately double the operating speed of an equivalent converter that doesnt utilize the technique. A marked improvement in the speed of analog to digital converter is achieved by the present invention with multiple level correction as compared with the single level correction technique.

SUMMARY The present invention utilizes an analog to digital converter which comprises a four stage block of multielement comparators using a level correction technique to achieve full stage subranging of multilevel inputs. A complete I I bit word is generated by combining the output of the four stages. The first section generates a 3 bit word, the second section generates the next 3 bits, the third section generates the next 3 bits, and the fourth section generates the last 2 bits. Synchronization of the outputs of the four comparator sections provides time alinement in a final output register thus creating the complete ll bit word.

It is one object of the invention, therefore, to provide an improved analog to digital converter apparatus utilizing a four stage subranging converter with multiple level error correction.

It is another object of the invention to provide an im proved analog to digital converter apparatus having a substantially more rapid acquisition of the subrange words, thus increasing the speed of the overall conversion.

These and other advantages, features and objects of the invention will become more apparent from the following description taken in connection with the illustrative embodiment in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the analog to digital con- 6 FIG. 3 is a graphic representation of an ideal input voltage to the converter apparatus versus time, and

FIG. 4 is a graphic representation of an input voltage to the converter apparatus that varies with time.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, there is shown an I I bit, 2 MHz word rate converter apparatus utilizing subranging with digital error correction. The subranging mechanization for this converter generates the 11 bit word in four sections. The first section A generates a 3 bit word (SIGN, MSB, MSB-l). The second section B generates the next 3 bits. The third section C generates the next 3 bit word, and the fourth section D generates the last 2 bits (LSB +1, LSB). These groups of 3, 3, 3, and 2 bits are aligned in time in the final output register 10 creating the complete eleven bit word.

The conversion process is as follows: The input video which is scaled from i 8.188 to i 2.047 V, is sampled at the beginning of a 500 nsec range bin and is converted in the four stages A, B, C and D with a conversion time of approximately nsecs per stage.

The first section A determines the word in the first 3 bits (SIGN, MSB, MSB-l) by dividing the dynamic range (i 2,047 mv) into eight equal segments with seven voltage comparators 12. The magnitude of a particular input signal is sensed by these comparators. Once the comparators l2 determine which segment contains the input signal, a voltage proportional to the lower bound of that segment is subtracted from the input signal in the section A residue amplifier 14.

The outputs of the comparators 12 are defined such that if the input voltage exceeds (more positive) the reference voltage of a comparator, the output of that comparator will be false. Once the input voltage has settled within accuracy limits (i I28 mv) determined by the self correction (redundancy) requirements, the outputs of the comparators 12 are latched. Once the section A outputs are latched, the A Vres equation will be used to determine the output voltage of section A Residue Amplifier 14.

A Vres =2 (Vin) NA (1024) 3584 where NA the number of comparators switched in the true state, not counting ACO or AC8 since they are used only for gross overvoltage sensing. The output of the Section A, Residue amplifier 14 is the input to the Section B Comparators l6 and Residue card 18.

The Section B Comparators 16 contains eleven comparators biased as shown in Table 1 shown below.

The outputs of the comparators are defined as follows:

If the input voltage (A Vres) exceeds (more positive) the reference voltage, the output of that comparator will be false. Comparators BC00, BCO, 8C8, and BC88 are the redundancy comparators. The redundancy comparators would not be necessary if it could be guaranteed that the decision made by the A Comparators 12 was correct. Since it is required that the input voltage settle to within 128 mv of the final value, an error is possible. If a section A comparator 12 is latched in an incorrect state, this error will be reflected in the output of the section A Residue amplifier 14. This error will be sensed by the section B redundancy comparators 16. If a redundancy comparator senses an error, it will generate a command to the digital correction circuitry which will correct the binary count that has been decoded from the section A comparators l2.

Add 1 command: Set the decoded binary output to 000 and add I to the previous stages.

Add 2 command: Set the decoded binary output to and add I to the previous stages. 5 Analog Conditions for Correct Operation Reflecting the errors back to the input,

Vin must settle to within I28 mv before ACO-AC8 may be latched.

Vin must settle to within i 16 mv before BC00-BC88 may be latched.

Vin must settle to within i 4 mv before CC00-CC88 may be latched.

Vin must settle to within 1' L0 mv before DC00 DC88 may be latched.

The output of section B Residue amplifier 18 is defined y B vres 8 (A vres) NB (1024) 5632 The following two examples will be shown to demonwhere NB the number of comparator Switches in the strate the operation of the converter. Example I will true State including 8C0 Bcoo RC8 and BC88 assume an ideal input voltage which is showing FIG. 3.

9 i t The operation of Section C Comparators 20 and Res- 2 assum? an mpm that vanes idue amplifier 22 is identical to the operation of section 20 (shown 4) causmg errors to P made dunng the B comparators The operation of the Section D converslon. The second example will demonstrate the Comparators 24 is identical to sections B and C com- Redundancy correction P parators. The timing diagram for the A/D converter EXAMPLE I shown in FIG. 1 is given in FIG. 2. The threshold voltages for the section A-D comparators l2, l6, 18, 24 is 25 Input given by tables 2 through 4. The desired output word will equal in magnitude Table 2 [1,476 mv/2 mv (LSB) 738 AC8 2048 mv Ex 2 AC7 I536 mv G Ex 1 N 2% i'gf; l l0] I 100010 AC4 O V 25; 3;: Vin to Comparators A and Residue Amplifier A card AC] l536 mv equals 1,476 mv. The l mv offset is added in the sam- Afl] 2048 ple and hold card and is required to center the voltage between comparator states and give a symmetrical dynamic range. The values of Vin are shown in FIG. 3. Table 3 40 Table 2 above shows comparators AGO-AC6 False and AC7-AC8 True, NA 1. This condition decodes C E 2 640 to the binary word NO.

X cca 512 m CC, 384 Section A CC6 256 mv 5 Data Correction CC3 [28 my I ID No Overvoltage CCZ 256 mv Condition CC] 384 mv Ex 1 AVres =-2 (1476 l)l (1024 3584 CCO s12 mv 2954 1024 3534 CCOO 640 mv AVres 394 mv Table 4 Table 1 above shows Comparators BC88 BC 8 False, BC7 BC00 True. NB 9. This condition decodes to DCOO +768 my the binary word 1 l l. 32:? I Section B DC4 O V 0C6 Ex 1 Ex 2 256 my Data Correction C- 0C3 5 l2 mv l l I No Correction 768 BVres s (-394) 9 (1024) 5632 =+3l52 92l6 5632 BVres 432 mv The following are the rules for digital correction:

Subt 2 command: Set the decoded binary output to 6 and subtract 1 from the previous stages.

Subt I command: Set the decoded binary output to 11 l and subtract 1 from the previous stages.

5 Table 3 above shows Comparators CC00 CCO False. CC] CC88 True. NC 9. This condition decodes to the binary word 000.

Section C Data Correction Command 000 No Corrections CVres 8 (432) 9 (1024) 5632 +3456 9216 5632 CVres =l28 mv Table 4 above shows Comparators DC88 DC6 False. l

DC4-DC00 True.

1011100010 738 as required The Example 1 demonstrates the operation of the converter assuming an idealized video input. Example 2 will be more realistic in that the amplitude of Vin will be changing with time. This will necessitate a recalculation of the residue amplifier outputs each time a comparison is made.

For value of Vin shown in FIG. 4, Table 2 shows Comparators ACO AC7 False, AC8 True. NA 0. This condition decodes to the binary word 11 1. Note: The decoded word is in error by 1 bit.

Section A Correction Command No Overvoltage Condition Data Using the value of Vin at B comparators, Latch Time AVres =2 (1,461 1) (1,024) 3,584

AVres 2,924 3,584

AVres +660 mv Table 1 above shows Comparators BC88 BC00 False. No comparators in the True state. NB 0. This condition generates a subtract 2 command. As described in Rules for Digital Correction," this condition will force the decoded word to 110 and generate a subtract 1 command to Section A.

Section B Data Correction Command 110 Subtract 1 from Section A tion," this condition will force the decoded word to 000 and generate an Add 1 command to Section B.

Section C Data Correction Command 000 Add 1 to Section 13 Using the value of Vin at D comparators latch time, AVres and BVres are recalculated to solve for CVres.

AVres 2 (1,476 1) 0 (1,024) 3,584 AVres +630 BVres =--8 (630) 0 (1,024) 5,632 BVres +592 CVres 8(592) 1 (1,024) 5,632 CVres 4,736 1024 +5,632 CVres 128 mv Table 4 above shows Comparators DC88 DC6 False. DC4-DC00, True.

Section D Data Correction Commands 10 No Correction Summary of Output Conditions Section A Section B Section C Section D 111 No 1 10 Subtract 000 Add 1 10 No Overvoltage 1 from A to B Correction Final Output Word 1 l0 1 1 l 000 10 The final output word agrees with the idealized output for Example 1. This example demonstrates how the redundancy information is used.

The various elements and devices which comprise the present invention are available from the following source. For example, the comparator A and its associated binary decode matrix are available as a unit under part number 1599271 from Hughes Aircraft Corp., Fullerton, Calif. 92634. The section B and C comparators respectively and their associated binary decode matrix are available under part number 1599272 from Hughes Aircraft Corp., Fullerton, Calif. 92634. The section D comparator and its binary decode matrix is available under part number 1599273. The following components are also available from Hughes Aircraft Corp., Fullerton, Calif. 92634 under the following part numbers as specified, for example; the residue A unit comprising the seven analog switches, the offset 3584, and the A residue amplifier under part number 1599275; the residue B unit and residue C unit both respectively comprising 1 l analog switches, the offset 1408 and the B and C residue amplifier respectively under part number 1599276; the digital correction unit comprising the error command transfer logic, the binary word registers, the command registers, the digital error correction, and the output register under part number 1599279; the scale amplifier has part number 1599281; and the sample in hold has part number 1599278. All of the above components are available under the given part numbers from Hughes Aircraft Corp., Fullerton, Calif. 92634.

Although the invention has been described with reference to a particular embodiment, it will be understood to those skilled in the art that the invention is capable of a variety of alternative embodiments within the spirit and scope of the appended claims.

utilized by said digital error correction unit to correct said binary word output, and

an output register connected to said digital error correction unit to receive said binary word output,

We claim:

1. An analog to digital converter apparatus with digital error correction comprising in combination:

an analog to digital converter having four stages to generate an I I bit word, said analog to digital converter receiving an input voltage signal, said first state generating a 3 bit word, said second and third stages each generating a 3 bit word, said fourth stage generating a 2 bit word, said analog to digital converter providing an output binary count, said second, third and fourth stages including a plurality of redundancy comparators, (said plurality of redundancy comparators respectively checking the output of the previous stages) said plurality of 2. An analog to digital converter apparatus as described in claim 1 wherein said first stage ofsaid analog 10 to digital converter comprises:

seven voltage comparators to determine the first segment of said I I bit word, said first segment being applied to a first residue amplifier, said first residue amplifier subtracting a voltage proportional to the redundancy Comparators respectively generating l5 lower bound of said first segment from said input a CorrectiOn command for the affected Stage upon voltage signal, said first residue amphfier providing sensing an error therein, f first output Voltageg I a piuramy of decode logic units respectively com said second stage of said analog to digital converter nected to said four stages of said analog to digital cqmpflsmg eleven Voltage comp arators F converter to receive the respective word bit, said mme second segment l bmary plurality of decode logic units respectively decodword Second Stage S Output ing said output binary count, said plurality of devoltage Secoml 3egmem bemg PP! to a Code logic units providing a binary word Output, second rest due amplifier, said second residue amsaid plurality of decode logic units respectively inplfier F f first f P Voltage 531d eluding error command logic units connected 0nd residue amplifier providing a second output oltage spectively to said plurality of redundancy compara- I tors of said second, third and fourth stages of said Sam thlrflstage sald analog to converter analog to digital converter, said error command ccfmpr'smg F voltage comparators l logic units respectively providing an error correcmme i Segment eleven bmary tion Signal upon receipt of said Correct command word, silldllllllq stage receiving said second output from one of said plurality of redundancy comparal Phlrd Segmen} bemg PP Q 3 [mm tors residue amplifier, said third residue amplifier rean interim holding register connected to said pluralcewmg Sald Seconcl P Yolmge, thrd ity of decode logic units to store said binary word f ampl'fier l a thlrd R Voltage, and Output said fourth stage of said analog to digital converter a digital error correction unit connected to said incqmpnsmg Seven Voltage q f o to deter terim holding register to receive said binary word i the fourth l' i 1 l l bmary word output, said digital error correction unit receiving fOPrth Stage recelvmg sald th'rd P"? Volt error correction signals from said plurality of de- Bald fourth Stage generatmg 2 word code logic units, said error correction signals being 40 

1. An analog to digital converter apparatus with digital error correction comprising in combination: an analog to digital converter having four stages to generate an 11 bit word, said analog to digital converter receiving an input voltage signal, said first state generating a 3 bit word, said second and third stages each generating a 3 bit word, said fourth stage generating a 2 bit word, said analog to digital converter providing an output binary count, said second, third and fourth stages including a plurality of redundancy comparators, said plurality of redundancy comparators respectively generating a correction command for the affected stage upon sensing an error therein, a plurality of decode logic units respectively connected to said four stages of said analog to digital converter to receive the respective word bit, said plurality of decode logic units respectively decoding said output binary count, said plurality of decode logic units providing a binary word output, said plurality of decode logic units respectively including error commaNd logic units connected respectively to said plurality of redundancy comparators of said second, third and fourth stages of said analog to digital converter, said error command logic units respectively providing an error correction signal upon receipt of said correct command from one of said plurality of redundancy comparators, an interim holding register connected to said plurality of decode logic units to store said binary word output, a digital error correction unit connected to said interim holding register to receive said binary word output, said digital error correction unit receiving error correction signals from said plurality of decode logic units, said error correction signals being utilized by said digital error correction unit to correct said binary word output, and an output register connected to said digital error correction unit to receive said binary word output, said output register aligning said binary word output in time, said output register providing a final 11 bit output word.
 2. An analog to digital converter apparatus as described in claim 1 wherein said first stage of said analog to digital converter comprises: seven voltage comparators to determine the first segment of said 11 bit word, said first segment being applied to a first residue amplifier, said first residue amplifier subtracting a voltage proportional to the lower bound of said first segment from said input voltage signal, said first residue amplifier providing a first output voltage, said second stage of said analog to digital converter comprising eleven voltage comparators to determine the second segment of said 11 bit binary word, said second stage receiving said first output voltage, said second segment being applied to a second residue amplifier, said second residue amplifier receiving said first output voltage, said second residue amplifier providing a second output voltage, said third stage of said analog to digital converter comprising eleven voltage comparators to determine the third segment of said eleven bit binary word, said third stage receiving said second output voltage, said third segment being applied to a third residue amplifier, said third residue amplifier receiving said second output voltage, said third residue amplifier providing a third output voltage, and said fourth stage of said analog to digital converter comprising seven voltage comparators to determine the fourth segment of said 11 bit binary word, said fourth stage receiving said third output voltage, said fourth stage generating a 2 word bit output. 